Low power design for adders

Low power design for adders

I have to implement a circuit that performs A+B+C+D serially.
A and B are added using the first adder, the result is added to C using
the second adder and finally the result is added to D using the third
adder, one after the other.
The problem is, in order to make the design low power. I have to turn off
the other two adders which are not in use. All I can think is Enable and
Disable signals, but this causes latency issues.
How do I synthesize this in in an effective manner in verilog?
A,B,C,D may change every clock cycle. a start signal is used to indicate
when a new calculation is required.